One of the challenges faced by high-speed digital designers is dealing with overshoot, undershoot, mismatched impedance ringing, jitter distribution, and crosstalk on their boards. These issues can be classified as signal integrity. Many high-speed designers use the Input/Output Buffer Information Specification (IBIS) modeling language to anticipate and resolve signal integrity issues. This modeling language has been widely used since the 1990s and has evolved into a formal standard: EIA-ANSI 656-B. The 5th edition of the IBIS Forum's August 2008 standard is still prevalent. IBIS uses current-voltage (IV) and voltage-time (Vt) data sheets to describe the I/O pin characteristics of a device. Vendors generate these tables by simulating or measuring their device I/O units. For high-speed designs that now have clock frequencies of up to 20 Gbits/sec, I can understand the need for such system simulation tools. IBIS makes SPICE simulation options less important because simulation time is much shorter and has the same accuracy. The IBIS simulation time I'm talking about is shorter than a large PCB system that takes days or weeks to complete a transistor-level SPICE simulation. It takes only a few minutes or hours to perform an IBIS simulation. With one IBIS simulation, you can generate many transmission line responses and eye diagrams. The IBIS format has demonstrated its value in the high-speed application industry. However, what really surprised me was that our customers are now asking for IBIS support for lower frequency devices such as clock devices below 40 MHz. Initially, I thought that component engineers have been trying to standardize their checklists. Now, I am not so sure. Even at lower frequencies, we face many signal integrity issues due to the digital signal edge rate. These fast edge rates are responsible for the ringing of the clock signal, causing a misinterpretation of a command or even an ADC burst 2 gain. IC vendors have very sophisticated SPICE simulation macro models for precision devices, but they are keeping up with our IBIS digital I/O model library. Figure 1 depicts a very efficient example of an IBIS model simulation. Figure 1: ADC processor clock signal (CH3) and data signal (CH12) of the ADC on the processor. In Figure 1, the designer did not pay attention to the line impedance. This figure shows the measured results of the ADC in the system. The ADC and processor are on their respective boards, and the designer simply connects the two boards together through a 1 meter long CAT-5 twisted pair. In Figure 1, the processor's clock signal frequency (CH3) is 2.25 MHz. The ADC uses this signal to synchronize the data transfer back to the processor (CH2). Initially, designers thought that the slow clock speed between the two devices would not cause termination problems. However, the clock and data signal termination methods create many signals that exceed the specified high and low thresholds (overshoot and undershoot), have false edge (ringing) signals, and reduce the operating margin (weakened eye diagram). signal of. IBIS simulation to help! Save time and reduce costs before you implement your circuit as hardware. Before you prototype, when you simulate a design, the IBIS model provided by the vendor and the model of your board are all useful in your toolbox. Signal integrity issues can affect both your high-speed and low-speed systems. With early stage simulation circuit analysis, you can apply many different conditions to your system to prevent and detect common signal integrity issues.
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